1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more specifically, to a method for fabricating a capacitor in a dynamic random access memory (DRAM) cell.
2. Description of Related Art
DRAM is an important integrated circuit which has been widely utilized in the electronic information industry. Referring to FIG. 1, a DRAM cell includes a transistor T and a capacitor C. The source of the transistor T is connected to a corresponding bit line BL. The drain of the transistor T is connected to a storage electrode of the capacitor C. The gate is connected to a corresponding word line WL. An opposed electrode of the capacitor C is connected to a constant voltage source. There is a dielectric layer between the storage electrode and the opposed electrode. As known to those skilled in the art, the capacitor C is provided for data storage. Therefore, a large capacitance of the capacitor C is required for preventing data loss and improving the refresh rate.
In a conventional DRAM circuit which has fewer than 1 MB cells, a two-dimensional capacitor structure is utilized for data storage. This capacitor is known as a planar-type capacitor. However, the planar-type capacitor requires a very large base area; otherwise, the capacitance is insufficient. The structure is therefore inapplicable for a highly-integrated DRAM circuit. Accordingly, certain three-dimensional capacitor structures have been developed to satisfy the requirements of the high-integrated DRAM circuit which has, for example, more than 16M cells. Among the three-dimensional structures, a trench-type structure and a stack-type structure are the most popular. However, defects are unavoidably generated in the semiconductor substrate of a trench-type capacitor, thus increasing the leakage current. Moreover, as the aspect ratio of a trench increases, the etching rate of the trench is reduced, thereby affecting the productivity of the trench-type capacitor. Therefore, the trench-type capacitor is commercially not that popular as the stack-type capacitor which is free of the problems mentioned above. Many newly-developed techniques are modifications of the stack-type capacitor for the purpose of reducing device dimensions.
In order to increase the capacitance of a capacitor, the thickness of the dielectric layer should be reduced or the electrode surface area has to be increased. As the dielectric layer has been made as thin as possible, and has reached the physical limitation of about 50 .ANG. below which direct carrier tunneling will occur to affect the performance of the capacitor, efforts have been made to improve the capacitance by expanding the electrode surface area.
Among the modifications to the stack-type capacitor structure, a easy and effective method in which the electrode is formed to have a rugged surface has been developed to increase the surface area. However, since the rugged surface is formed before patterning the electrode, only the top region of the electrode retains the rugged structure. The rest of the rugged surface has been etched after the electrode patterning. The improvement of the surface area and the capacitance is therefore limited.
The steps of a conventional DRAM fabrication method will be described in accompaniment with FIG. 2A through FIG. 2C. Referring to FIG. 2A, the DRAM is fabricated over a semiconductor substrate 10 which is, for example, a silicon substrate. An active region is defined over the semiconductor substrate 10 by a field oxide layer 11. Then a gate oxide layer 12, a polysilicon layer 13 and a insulating layer 14 are successively formed over the substrate 10 and are patterned to be a gate structure. The gate structure is utilized as a mask for ion implantation, thereby forming lightly-doped regions 15a and 15b in the semiconductor substrate 10. Moreover, a spacer 16 is formed on sidewall of the gate structure by depositing and etching back a dielectric layer. The spacer 16 and the gate structure are further utilized as a mask for implanting ions in the semiconductor substrate 10, thereby forming heavily doped regions 17a and 17b. A transistor including a gate, a drain and a source region is therefore formed over the semiconductor substrate 10.
The structure of FIG. 2A is then covered by a first insulating layer 18 which is, for example, a deposited BPSG layer. The first insulating layer 18 is patterned to have a contact opening 19 (shown by dashed line in the figure) in which the source region 17a of the transistor is exposed. The contact opening 19 is filled with a conducting layer which electrically connects the source region 17a and extends over the insulating layer 18. The conducting layer is then patterned to be a bit line 20 of the memory device. Moreover, a second insulating layer 21 such as a BPSG layer is deposited over the first insulating layer 18 and the bit line 20. The second insulating layer 21 and the first insulating layer 18 are then both etched to form another contact opening 22 to expose the drain region 17b of the transistor.
The contact opening 22 is then filled with another conducting layer 23 which can be a doped polysilicon layer. The polysilicon layer 23 electrically contacts the drain region 17b of the transistor and extends over the BPSG layer 21. Then a thin conducting layer 24 with rugged surface is deposited over the conducting layer 23. The thin layer 24 can be a polysilicon layer formed by the low-pressure chemical vapor deposition (LPCVD) method.
Referring to FIG. 2B, the thin conducting layer 24 and the conducing layer 23 are patterned according to the capacitor region by a micro lithography method and etching method, thereby forming a storage electrode 25 which consists of the conducting layer 23a and the thin conducting layer 24a.
Referring to FIG. 2C, a dielectric layer 26 is formed over the storage electrode 25 and the exposed surface of the second insulating layer 21. The dielectric layer 26 can be an oxide layer, a nitride layer, a Ta.sub.2 O.sub.5 layer or a ferroelectric layer. Moreover, another conducting layer such as a CVD polysilicon layer is formed over the dielectric layer 26 and is patterned to be an opposite electrode 27 of the capacitor.
Obviously, the aforementioned fabrication method of a DRAM device forms the thin rugged layer 24 prior to patterning the storage electrode 25 of the capacitor. Therefore, the rugged structure exists merely on the top surface of the storage electrode 25. Since the sidewall of the storage electrode 25 has no rugged structure, the improvement of the capacitance is limited.